1. Field
The present invention relates generally to the field of semiconductor manufacturing. More specifically, the present invention relates to a method of forming a silicon oxynitride (SiON or SiOxNy) gate dielectric and integrating it into a gate stack using Rapid Thermal Process (RTP).
2. Description of the Related Art
Integrated circuits are made up of literally million of active and passive devices such as transistors, capacitors and resistors. A transistor 100 generally includes a source 102, a drain 104, and a gate stack 106. The gate stack (FIG. 1) consists of a substrate 108 (e.g., typically made of silicon) on top of which is grown a dielectric 110 (typically made of silicon dioxide (SiO2)) and this is capped with an electrode 112 (made with a conductive material such as polycrystalline silicon).
In order to provide more computational power, the trend is to scale down transistors by shrinking device geometry. Moore's law scaling requires that the gate drive current must increase in order to increase the speed of the transistor. The gate drive current give by equation (1) can be increased by increasing the gate capacitance (Cox), which in turn (as shown by equation (2)) can be increased by either decreasing the dielectric thickness (d) or using a dielectric that has higher dielectric constant (k) than the existing SiO2 dielectric (k=3.9).
                                                        I              D                        ~            μ                    /          Lg                *                                            C              ox                        ⁡                          (                                                V                  DD                                -                                  V                  TH                                            )                                2                                    (        1        )                                          C          ox                =                  kA          d                                    (        2        )            where ID is the Drive Current; u is the Carrier Mobility, Lg is the gate length, Cox is the Gate Capacitance, VDD is the Opening Voltage; VTH is the Threshold Voltage; k is the dielectric constant, d is the dielectric thickness, and A is the device area.
To avoid complex integration and materials handling issues, device manufacturers would like to scale the device parameters as much as they can by decreasing the dielectric thickness. However lowering the SiO2 thickness below 20 Å results in poor gate reliability due to increase in tunneling current, increase in boron penetration into the substrate and poor process control for very thin oxide. While in theory the alternative of using a higher k gate dielectric appears very attractive, the material compatibility with the underlying Si substrate and the polysilicon gate electrode cannot be matched to what is provided with SiO2. Additionally, using SiO2 eliminates many materials handling contamination issues that must be dealt with when introducing rare-earth oxide as gate dielectrics.
Challenges encountered in extending SiO2 to 0.1 μm technology node and beyond, include (1) boron penetration in a transistor such as a PMOS device with a P+ boron (B) doped gate electrode into the gate oxide and underlying Si substrate. And, (2) increasing gate leakage current with decreasing gate oxide thickness.
Nitridation of the SiO2 layer to form silicon oxynitride (SiOxNy or alternatively SiON) has evolved as a promising candidate to scale the SiO2 dielectric down to 0.1 μm device generations. Incorporating nitrogen into the dielectric film blocks boron as well as increases the dielectric constant of the gate dielectric. The increase in the dielectric constant means a thicker dielectric can be used in comparison to pure SiO2 hence reducing gate leakage. For the nitrogen (N) doping to be effective in circumventing the challenges described above in ultra-thin (e.g., 12 Å) gate dielectrics, it is essential to have high (≧5%) total concentration of nitrogen in the dielectric film with the peak of the nitrogen concentration profile at the top surface of the gate dielectric.
Traditionally, thermal processes have been carried out in furnaces that process multiple wafers (5-100) at once. The furnaces have large volumes and it is difficult to pump out this huge volume. This coupled with the fact that the growth rate of most of the thermal processes goes down with decrease in process pressure has resulted in thermal processes usually being carried out at atmospheric (760 Torr) or slightly below atmospheric (>500 Torr) pressure.
Thermally grown silicon oxynitride has been used as gate dielectrics for several years from the 0.2 μm to 0.13 μm device generations. As the device technology has advanced from 0.2 μm to 0.1 μm the gate oxide has thinned from >25 Å to <12 Å. Hence, in order to block boron and reduce gate leakage the amount of nitrogen in the film has to be increased from <3% to 5-10%. When nitric oxide (NO) and nitrous dioxide (N2O) are used to grow the oxynitride gate dielectric the N gets incorporated in the dielectric film simultaneously as the oxynitride grows, hence nitrogen is distributed evenly in the film. If NO or N2O are used to form silicon oxynitride by annealing an existing SiO2 layer at elevated temperatures, the nitrogen incorporated by growing SiON at the Si-substrate/Oxide interface. Hence, nitrogen is incorporated at this interface. The amount of nitrogen in the later case (<2%) is less than in the former case (4-5%).
Silicon oxynitride grown directly with N2O or formed by annealing an SiO2 film with N2O has been the favored candidate for higher technology generations (0.2 μm) devices. The <2% nitrogen in the film was sufficient to enhance the device performance with >25 Å thick gate dielectric. As the device technology advanced to 0.13 μm, the nitrogen in the film had to be increased from <2% to 4-5% by using NO direct growth or NO anneal, in order to reduce the leakage current in comparison to the undoped SiO2 and prevent boron from diffusing through the thinner dielectric into the substrate. The amount of nitrogen incorporated by either one of these techniques is insufficient and the nitrogen concentration profile is inappropriate for extending SiON to 0.1 μM device generation as explained earlier. Lowering the process pressure would only reduce the rate of nitrogen incorporation into the film, hence the nitridation processes continued to be carried out at elevated pressures.
More recently, plasma nitridation has been used to nitride (to incorporate nitrogen into) the gate oxide. This technique results in high nitrogen concentration at the poly gate/oxide interface, which prevents boron penetration into the oxide dielectric. At the same time, the bulk of the oxide dielectric gets lightly doped with unassociated nitrogen during the plasma nitridation process, which reduces the electrical oxide thickness (EOT) over the starting oxide. The plasma nitridation process requires plasma hardware that can among other things cause metal contamination and plasma damage to the device and is difficult to maintain as compared to the traditional thermal processing hardware optimized for the front end processing. The challenges that plasma nitridation currently faces is scaling of device parameters Electrical Oxide Thickness (EOT) to <11 Å, Mobility degradation and lowering of Drive Current (Idsat) with ultra-thin dielectric (starting oxide <10 Å) for high performance application.
Another more recently adopted option has been thermal ammonia (NH3) anneal which has been demonstrated to incorporate nitrogen in the excess of 5% and under certain process conditions can result in higher nitrogen content at the surface of the dielectric than at the interface. This chemistry however has not been as popular as the NO or N2O chemistries for several reasons. The NH3 chemistry was production worthy when using furnaces for the thermal nitridation, as O2 or moisture (H2O) contamination even at the ppm level can prevent the incorporation of nitrogen in the film or give inconsistent results. In the case of furnace processing during the loading of wafers, large volumes of air and moisture enters the furnace which takes considerable amount of time to be removed resulting in inconsistent incorporation of nitrogen in the film in the wafers from the edge of the furnace to the center of the furnace. Unlike the NO and N2O chemistries, NH3 anneal results in hydrogen incorporation in the dielectric which results in hot electrons and results in device reliability issues. It has been shown that the hydrogen in the silicon oxynitride film can be eliminated by a post nitridation anneal at elevated temperatures for short times in either inert (N2 or Ar) or O2 ambient.
With the advent of Rapid Thermal Processing (RTP) and its integration with other process chambers in a cluster type tool, the NH3 process has become production worthy since the film can be efficiently nitrided in a controlled ambient without an O2 or H2O contamination as well as hydrogen in the film can be eliminated by RTP anneal. However the problems of the interfacial peak still remain. In the existing art, a base oxide SiO2 film (grown in a single wafer RTP chamber or a furnace) is subjected to ambients containing either pure NH3 or mixture of NH3 and inert gas (N2 or Ar) at elevated temperatures (>850° C.) and atmospheric (760 Torr) or sub atmospheric (>500 Torr) pressures. It has been observed, however, that this results in a bimodal distribution of nitrogen within the starting SiO2 film, with one nitrogen peak at the silicon oxynitride surface (or sometimes at the polysilicon cap/silicon oxynitride interface and a second peak at the silicon oxynitride/substrate interface. Such bimodal distribution has been observed even at reaction pressures as low as 100 Torr. The first peak is responsible for imparting good electrical properties to the device such as boron blocking and increasing the dielectric constant, thereby decreasing the leakage current in the device as compared to the starting oxide of similar electrical thickness. The second peak on the other hand imparts poor interfacial properties to the gate stack resulting in larger threshold voltage shifts and mobility degradation of charge carriers in the transistor.
The kinetics of thermal nitridation of gate oxide with NH3 has been studied for 80-100 Å gate oxides. For the silicon oxynitride dielectric film to be useful in the 0.1 μm device technology node and beyond the thickness has to be <25 Å in the low leakage transistor devices and <12 Å for high performance transistors. The high pressure NH3 process currently used for the silicon oxynitride formation will cause a high concentration of nitrogen at the silicon oxynitride/substrate interface resulting in poor device performance, limiting the scaling of this process at 0.1 μm technology and beyond.